Parallel Architectures for Real Time Systems (PARTS)

Parallel Architectures for Real-Time Systems (PARTS) is transdisciplinary research center active in the domain of analysis, design and implementation of real-time systems for embedded applications.

Adopted approach is based on the extension of the well known co-design paradigm: to the concept of simultaneous SOFTWARE/HARDWARE design, we append the aspects of TECHNOLOGY used for integrated circuit manufacturing. By exploiting SOFTWARE/ HARDWARE/TECHNOLOGY triplet, the goal is to holistically design predictable, optimized and efficient parallel real-time systems.

SOFTWARE aspects cover fundamental research, practical design and implementation of advanced scheduling algorithms for Multi-Processor real-time operating systems (RTOS). These algorithms perform smart task handling and are able to take into account multiple constraints simultaneously. Typically, these algorithms manipulate: execution time, power dissipation, thermal aspects, etc. Since we are targeting fully integrated systems, application mapping, off-line/on-line resource optimization are also taken into account.

HARDWARE part consist in the design and implementation of Multi-Processor Systems-on-Chip (MPSoC). The MPSoC platforms use for processing elements and memory existing building blocks. For systems with higher degree of parallelism, the communication is covered by Network-on-Chip (NoC). However, in order to enhance the performance of the system as a whole, and the Operating System in particular, i.e. scheduler, dedicated hardware services are developed and integrated into existing components on both computational and communicational (NoC) components. The requirements for these services are typically set during task scheduler design time.

Finally, the whole process is TECHNOLOGY aware. Emerging technologies for advanced integrated circuit manufacturing and packaging, such as 3D-Stacked Integrated Circuits, are offering enormous potential for design of complex, highly optimized, and heterogeneous systems (memory-on-logic, logic-on-logic etc.). The design of the specific operating systems schedulers and the MPSoC platforms take into account the potential advantages of such technologies for even more optimized real-time systems (for example by combining high-performance/high-power with low-performance/low-power integrated circuits dies in the same package).