Call for Participation: Heterogeneous Architectures and Real-Time Systems Seminar (FNRS Contact Group)

    From Fri 5 May 2017 10:00 to Thu 5 May 2016 17:00

    FNRS-logo Grascomp-logo

    A one-day seminar will take place within the framework of the Belgian FNRS Contact Group “Embedded Real-Time Systems” and the GRASCOMP doctoral school (Belgium's French Community).

    The workshop offers a round table for exchanging ideas and foster discussions around the theme of heterogeneous architectures and real-time systems, including (but not limited to): real-time scheduling, NoC, and embedded real-time electronics, among others.

    Free but mandatory registration (by May 1st 2017)

    Register here

    Program

    • 9:30am — Welcome
    • 10am — Keynote Talk

      “Real-Time Scheduling on Heterogeneous Multiprocessors”

      By Dr. Gurulingesh Raravi (University of Porto, Portugal)

      Abstract

      Heterogeneous processing platforms are spreading at an unprecedented rate in embedded systems thanks to the availability of multicore processors. These platforms span diverse areas of our life right from smart phones to health-care to autonomous vehicles. They have emerged as today's computational workhorse for both desktop and embedded systems; just like the single-core processor was in the past. Every major semiconductor company is offering heterogeneous multicore chips.

      Despite this widespread availability of heterogeneous multicore processors and the eagerness to use them, their use in embedded real-time systems is non-trivial. One of the major challenges is that many embedded systems have real-time requirements and it must be proven before run-time that these requirements are satisfied at run-time. The way applications are scheduled significantly influences whether their timing requirements are satisfied.

      The real-time community is starting to take some initial steps in developing scheduling algorithms and analysis techniques for heterogeneous multicores. This talk gives an overview of the on-going effort in the community in this direction. In particular, it will discuss a couple of solutions that have been recently proposed by researchers by highlighting the key techniques that were used in developing these solutions. It concludes by providing a glimpse of open problems.

      Bio

      Gurulingesh Raravi is currently a Research Associate at CISTER Research Centre in Porto. He received the Doctorate degree from University of Porto in 2014. He has worked in industry both prior to and after his PhD for about 5+ years in designing solutions for a variety of problems encompassing domains such as cyber-physical systems and services computing. His research interests include embedded real-time systems, resource allocation and sharing in distributed systems, algorithms, and optimisation.

    • 11:15am — Coffee break

    • 11:30 — “A Novel Architecture for Highly-Scalable, Secure, and Real-Time Systems-on-Chip.”, Soultana Ellinidiou, Xavier Poczekajlo, Gaurav Sharma, Georgios Bousdras, Jean-Michel Dricot, Joël Goossens, Olivier Markowitch, Dragomir Milojevic & François Quitin (ULB).
    • 12:00pm - “FPGA as Image Signal pre-Processors for Smart Cameras based Applications”, Naim Hard & Carlos Valderrama (UMons).
    • 12:30pm Lunch
    • 1:15pm — “Hard real-time scheduler for sporadic task sets on heterogeneous platforms, and multimode systems”, Xavier Poczekajlo & Joël Goossens (ULB).
    • 1:45pm - “Binding Design and Analysis by Viewpoints for Heterogenous Real-Time systems”, Anh-Toan Long, Yassine Ouhammou & Emmanuel Grolleau (ENSMA).
    • 2:15pm - “Mapping avionics functions on a mixed NoC/AFDX architecture”, Laure Abdallah, Jérôme Ermont, Jean-Luc Scharbard & Christian Fraboul (IRIT)
    • 2:45pm — Coffee break
    • 3:15pm — “Can we get a predictable cache system for real-time computer systems?”, Yannick Allard, Dragomir Milojevic & Joël Goossens (ULB).
    • 3:45pm — “Research and implementation challenges of RTOS support for heterogeneous computing platforms”, Martin Cornil, Antonio Paolillo, Joël Goossens & Ben Rodriguez (Hipperos/ULB).
    • 4:15pm Closing remarks

    Committee

    • Joël Goossens (ULB, Brussels, Belgium)
    • Pierre Manneback (UMons, Mons, Belgium)
    • Dragomir Milojevic (ULB, Brussels, Belgium)

    Venue

    The seminar will be held NO building (5th floor, Solvay room), “campus de la Plaine” ULB, Brussels.

    Access map

    By subway: Line 5, stop “Delta”.

    By train: fast trains (Thalys, TGV, Eurostar, ...), stop Bruxelles-Midi train station. Then subway Line 2 or 6, “Elisabeth” direction, exit at “Arts-Loi”, then line 5, “Hermann-Debroux” direction, stop at “Delta”. (about 1/2 hour).

    Hotel Suggestions:

    Important information

    Friday May 5th 2017.

    9:30am — 4:30pm

    Solvay room, ULB, plaine campus, building NO, 5th floor

    Follow this page parts.ulb.ac.be/pages/events.html#HARTS-ULB-2017 or contact the chair person (E-mail: joel.goossens@ulb.ac.be)

    Real-Time Networks Seminar (FNRS Contact Group)

    by Luis Almeida
    From Fri 27 May 2016 10:00 to Fri 27 May 2016 17:00

    FNRS-logo Grascomp-logo

    A one-day seminar will take place within the framework of the Belgian FNRS Contact Group “Embedded Real-Time Systems” and the GRASCOMP doctoral school (Belgium's French Community).

    The workshop offers a round table for exchanging ideas and foster discussions around the theme of real-time network, including (but not limited to): real-time message scheduling, Ethernet, CAN, FlexRay, networked embedded systems and sensor networks, among others. The format of the seminar encourages interaction between participants and open discussions.

    Free but mandatory registration (by May 19th)

    Register here

    Program

    • 9:30am — Welcome
    • 10am — Keynote Talk Prof. Luis Almeida (University of Porto, Portugal)

      Flexible Time-Triggered Switched Ethernet: Towards Flexible/Open Cyber-Physical Systems

      The Flexible Time-Triggered Switched Ethernet (FTT-SE) protocol was proposed in 2006 as a realization of the FTT paradigm specifically adapted to switched Ethernet. This paradigm is a framework to develop distributed real-time systems that are reconfigurable and adaptive. It has been successfully used for dynamic Quality-of-Service (QoS) management in control applications and video transmission, and for dynamic reconfiguration of real-time systems that are either open or include subsystems that operate occasionally. It is particularly suited to support dynamic and adaptive resource reservation in network resources through virtual channels.

      In the realm of real-time Ethernet protocols, FTT-SE flexibility features with real-time guarantees are unique, possibly comparable to much more costly solutions, only, such as layer 3 or 2.5 carrier grade switches with RSVP-TE or MPLS, AVBridges or Software-Defined Networks (SDNs).

      In this talk we highlight recent FTT developments in the context of switched Ethernet technology. We start with FTT-SE protocol basics and then discuss how to improve performance and robustness with the HaRTES switch that is an FTT-enabled Ethernet switch, as well as scalability and dependability of FTT-SE/HaRTES systems. We end with several use cases that show the features of these systems.

      Bio

      Luis Almeida is currently an associate professor at the Electrical and Computer Engineering Department of the University of Porto and a member of the Institute of Telecommunications in Porto where he coordinates the Distributed and Real-Time Embedded Systems Lab. He is also a member of the IEEE Computer Society, IFIP Tecnical Committee on Embedded Systems, EMSIG EDAA Special Interest Group on Embedded Systems Design (vice-chair), RoboCup Federation (trustee) and the Portuguese RoboCup National Committee (vice-president).

      His current interests are real-time communication protocols for Cyber-Physical Systems with an emphasis on mechanisms to support predictable operational flexibility as needed for dynamic QoS management, graceful degradation and open distributed real-time systems in general. He co-authored over 250 refereed publications, 4 patents and 10 book chapters. He regularly participates in the organization and program committees of scientific events in the Real-Time Systems, Industrial Systems and Robotics communities, including RTSS, ECRTS, DATE, SIES, WFCS, ETFA and RoboCup.

    • 11:15am — Coffee break

    • 11:30 — “Why and how to map real-time core-to-I/O flows over a Tilera-like Network on Chip?”, Laure Abdallah, Mathieu Jan, Jérôme Ermont & Christian Fraboul
    • 12:00pm Lunch
    • 1:00pm — “Bringing Dynamicity to Real-Time Systems Through the Use of Dynamic Mesh Networking”, Florian Greff, Ye-Qiong Song, Laurent Ciarletta & Arnaud Samama
    • 1:30pm — “Buffer Dimensioning based on FA Approach in the AFDX Context”, Nassima Benammar, Henri Bauer, Frédéric Ridouard & Pascal Richard
    • 2pm — “Reliability of CAN-Based Distributed Real-Time Systems”, Arpan Gujarapi & Björn B. Brandenburg
    • 2:30pm — Coffee break
    • We move to room “Forum F.”

    • 3:00pm — “FTT-OpenFlow, on the way towards real-time SDN”, Cédric Ternon, Jean-Michel Dricot & Joël Goossens
    • 3:30pm — “Extended Recursive Analysis for Tilera and KalRay-like NoC Architectures”, Hamdi Ayed, Jérôme Ermont, Jean-luc Scharbarg & Christian Fraboul
    • 4:00pm Closing remarks

    Venue

    The seminar will be held NO building (5th floor, Solvay room), “campus de la Plaine” ULB, Brussels.

    Access map

    By subway: Line 5, “Hermann-Debroux” direction, stop “Delta”

    By train: fast trains (Thalys, TGV, Eurostar, ...), stop Bruxelles-Midi train station. Then subway Line 2 or 6, “Elisabeth” direction, exit at “Arts-Loi”, then line 5, “Hermann-Debroux” direction, stop at “Delta”. (about 1/2 hour).

    Hotels

    Suggestions:

    Committee

    • Joël Goossens (ULB, Brussels, Belgium)
    • Pierre Manneback (UMons, Mons, Belgium)
    • Jean-Michel Dricot (ULB, Brussels, Belgium)

    Further information

    Friday May 27th 2016.

    9:30am — 4:30pm

    Solvay room, ULB, plaine campus, building NO, 5th floor

    Contact the chair person joel.goossens@ulb.ac.be

    Cycle de développement logiciel critique et temps réel : un exemple de mise en œuvre en avionique

    by Emmanuel Grolleau
    From Fri 3 Jun 2016 16:00 to Fri 3 Jun 2016 18:00

    année de la France

    Salle de vidéoconférence, UB2.129, campus du solbosh, ULB

    Professeur invité

    Emmanuel Grolleau, ISAE-ENSMA (Institut Supérieur de l'Aéronautique et de l'Espace, École Nationale Supérieure de Mécanique et d'Aéronautique), LIAS (Laboratoire d'Informatique et d'Automatique pour les Systèmes)

    Résumé de l'exposé

    Le secteur aéronautique et aérospatial est très développé en France, ce pays a développé un savoir-faire avec l'apparition du Concorde et de la Caravelle, savoir-faire depuis remisé sur l'ensemble des aéronefs d'Airbus. La recherche fondamentale et industrielle est dès lors très importante aussi et couvre un très large spectre. Nous nous intéressons ici à l'informatique, aux logiciels embarqués qui doivent dans ce secteur être certifiables et respecter des contraintes temporelles fortes. Dans cette présentation, nous considérons du logiciel embarqué critique et temps réel.

    Dans l'avionique, ainsi que dans de nombreux secteurs du logiciel embarqué critique, le cycle logiciel typique part d'exigences, puis exprime une décomposition fonctionnelle en utilisant une sémantique flots de données ou non, indépendamment du matériel sous-jacent. La conception du matériel/logiciel est la prochaine étape vers l'implémentation du système embarqué. Pour les systèmes critiques, typiquement en aéronautique, des langages de description d'architecture (ADL) sont utilisés pour décrire les interactions entre les différents artefacts logiciels et comment le logiciel est déployé sur le matériel. Une important étape de la conception est donc d'allouer les fonctions aux tâches, les tâches aux calculateurs(éventuellement aux partitions de calculateur pour ARINC 653), et les messages aux réseaux.Les ADL proposent des concepts qui sont proposés par la plupart des noyaux temps réels (RTOS). Lorsque les choix de conception sont effectués, il existe de plus en plus d'outils technologiques permettant de faciliter la génération automatique ou semi-automatique de code(model to text). Cette présentation se conclura par les différentes modélisations temporelleseffectuées à partir de la conception d'un système exprimé dans un ADL.

    Public visé

    L'exposé vise un large public avec des bases en sciences informatiques, cela comprend les étudiants de la Faculté des Sciences en informatique à partir du BA2, les étudiants de l'École polytechnique à partir du BA3 et les chercheurs en sciences informatiques.

    Informations pratiques

    le 3 juin 2016.

    de 16h à 18h.

    joel.goossens@ulb.ac.be